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september 2011 ? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates nc7sz57 / nc7sz58 tinylogic ? uhs universal configurable two-input logic gates features ? ultra high speed ? capable of implementing any two-input logic functions ? typical usage replaces two (2) tinylogic ? gate devices ? reduces part counts in inventory ? broad v cc operating range: 1.65v to 5.5v ? power down high impedance input/output ? over-voltage tolerant input s facilitate 5v to 3v translation ? proprietary noise/emi reduction circuitry implemented description the nc7sz57 and nc7sz58 are universal configurable two-input logic gates. each device is capable of being configured for 1 of 5 unique two-input logic functions. any possible two-input combinatorial logic function can be implemented, as shown in the function selection table . device functionality is selected by how the device is wired at the board level. figures 4 through 13 illustrate how to connec t the nc7sz57 and nc7sz58, respectively, for the desired logic function. all inputs have been implemented with hysteresis. the device is fabricat ed with advanced cmos technology to achieve ultra high speed with high output drive while maintaining low st atic power dissipation over a broad v cc operating range. the dev ice is specified to operate over the 1. 65v to 5.5v v cc operating range. the input and output ar e high impedance when v cc is 0v. inputs tolerate voltages up to 5.5v independent of v cc operating range. ordering information part number top mark package packing method nc7sz57p6x z57 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7sz57l6x kk 6-lead micropak?, 1.0mm wide 5000 units on tape & reel nc7sz57fhx kk 6-lead, micropak2?, 1x1mm body, .35mm pitch nc7sz58p6x z58 6-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel nc7sz58l6x ll 6-lead micropak?, 1.0mm wide 5000 units on tape & reel nc7sz58fhx ll 6-lead, micropak2? , 1x1mm body, .35mm pitch
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 2 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates pin configurations figure 1. sc70 (top view) figure 2. micropak? (top through view) figure 3. pin 1 orientation notes: 1. aaa represents product code top mark ( see ordering information ). 2. orientation of top mark determines pin one location. 3. reading the top mark left to right, pin one is the lower left pin. pin definitions pin # sc70 pin # micropak? name description 1 1 i 1 data input 2 2 gnd ground 3 3 i 0 data input 4 4 y output 5 5 v cc supply voltage 6 6 i 2 data input
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 3 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates function table inputs nc7sz57 nc7sz58 i 2 i 1 i 0 y = (i 0 ) ? (i 2 ) + (i 1 ) ? (i 2 ) y = (i 0 ) ? (i 2 ) + (i 1 ) ? (i 2 ) l l l h l l l h l h l h l h l l h h l h h l l l h h l h l h h h l h l h h h h l h = high logic level l = low logic level function selection table 2-input logic function device select ion connection configuration 2-input and nc7sz57 figure 4 2-input and with inverted i nput nc7sz58 figure 10, figure 11 2-input and with both i nputs inverted nc7sz57 figure 7 2-input nand nc7sz58 figure 9 2-input nand with inverted i nput nc7sz57 figure 5, figure 6 2-input nand with both i nputs inverted nc7sz58 figure 12 2-input or nc7sz58 figure 12 2-input or with inverted i nput nc7sz57 figure 5, figure 6 2-input or with both inputs inverted nc7sz58 figure 9 2-input nor nc7sz57 figure 7 2-input nor with inverted i nput nc7sz58 figure 9, figure 10 2-input nor with both i nputs inverted nc7sz57 figure 4 2-input xor nc7sz58 figure 13 2-input xnor nc7sz57 figure 8
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 4 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates nc7sz57 logic configurations figure 4 through figure 8 show the logical functions that can be implemented using t he nc7sz57. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logica l implementation is next to the board-level physical implem entation of how the pins of the function s hould be connected. figure 4. 2-input and gate figure 5. 2-input nand with inverted a input figure 6. 2-input nand with inverted b input figure 7. 2-input nor gate figure 8. 2-input xnor gate
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 5 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates nc7sz58 logic configurations figure 9 through figure 13 show the logical functions that can be implemented using the nc7sz58. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pi ns of the function should be connected. figure 9. 2-input nand gate figure 10. 2-input and with inverted a input figure 11. 2-input and with inverted b input figure 12. 2-input or gate figure 13. 2-input xor gate
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 6 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v cc supply voltage -0.5 7.0 v v in dc input voltage -0.5 7.0 v v out dc output voltage -0.5 7.0 v i ik dc input diode current v in < 0.5v -50 ma i ok dc output diode current v out < -0.5v -50 ma i out dc output source / sink current 50 ma i cc or i gnd dc v cc or ground current 50 ma t stg storage temperature range -65 +150 c t j maximum junction temperature under bias +150 c t l lead temperature, soldering 10 seconds +260 c p d power dissipation at +85c micropak?-6 130 mw sc70-6 180 micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charged device model, jedec:jesd22-c101 2000 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. units v cc supply voltage operat ing 1.65 5.5 v supply voltage data re tention 1.5 5.5 v in input voltage 0 5.5 v v out output voltage 0 v cc v t a operating temperat ure -40 +85 c ? ja ? thermal resistance sc70-6 350 c/w micropak?-6 500 micropak2?-6 560
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 7 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates dc electrical characteristics symbo l parameter v cc conditions t a =+25c t a =-40 to +85c units min. typ. max. min. max. v p positive threshold voltage 1.65 0.60 0.99 1.40 0.60 1.40 v 2.30 1.00 1.39 1.80 1.00 1.80 3.00 1.30 1.77 2.20 1.30 2.20 4.50 1.90 2.49 3.10 1.90 3.10 5.50 2.20 2.95 3.60 2.20 3.60 v n negative threshold voltage 1.65 0.20 0.50 0.90 0.20 0.90 v 2.30 0.40 0.75 1.15 0.40 1.15 3.00 0.60 0.99 1.50 0.60 1.50 4.50 1.00 1.43 2.00 1.00 2.00 5.50 1.20 1.70 2.30 1.20 2.30 v h hysteresis voltage 1.65 0.15 0.48 0.90 0.15 0.90 v 2.30 0.25 0.64 1.10 0.25 1.10 3.00 0.40 0.78 1.20 0.40 1.20 4.50 0.60 1.06 1.50 0.60 1.50 5.50 0.70 1.25 1.70 0.70 1.70 v oh high level output voltage 1.65 v in =v ih or v il i oh = -100a 1.55 1.65 1.55 v 2.30 2.20 2.30 2.20 3.00 2.90 3.00 2.90 4.50 4.40 4.50 4.40 1.65 v in =v ih or v il i oh = -4ma 1.29 1.52 1.29 2.30 i oh = -8ma 1.90 2.15 1.90 3.00 i oh = -16ma 2.40 2.80 2.40 3.00 i oh = -24ma 2.30 2.68 2.30 4.50 i oh = -32ma 3.80 4.20 3.80 continued on the following page?
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 8 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates dc electrical characteristics (continued) symbol parameter v cc conditions t a =+25c t a =-40 to +85c units min. typ. max. min. max. v ol low level output voltage 1.65 v in =v ih or v il i ol =100a 0.10 0.10 v 2.30 0.10 0.10 3.00 0.10 0.10 4.50 0.10 0.10 1.65 v in =v ih or v il i ol =4ma 0.08 0.24 0.24 2.30 i ol =8ma 0.10 0.30 0.30 3.00 i ol =16ma 0.15 0.40 0.40 3.00 i ol =24ma 0.22 0.55 0.55 4.50 i ol =32ma 0.22 0.55 0.55 i in input leakage current 0 to 5.50 v in ? 5.5v, gnd 0.1 1.0 a i off power off leakage current 0 v in or v out ? 5.5v 1 10 a i cc quiescent supply current 1.65 to 5.5 v in ? 5.5v, gnd 1 10 a ac electrical characteristics symbol parameter v cc conditions t a =25c t a =-40 to 85c units figure min. typ. max. min. max. t phl , t plh propagation delay i n to y 1.8 0.15 c l =15pf, r l =1m ? 3.0 8.0 14.0 3.0 14.5 ns figure 14 figure 16 2.5 0.2 1.5 4.9 8.0 1.5 8.5 3.3 0.3 1.2 3.7 5.3 1.2 5.7 5.0 0.5 0.8 2.8 4.3 0.8 4.6 3.3 0.3 c l =50pf, r l =500 ? 1.5 4.2 6.0 1.5 6.5 5.0 0.5 1.0 3.4 4.9 1.0 5.3 c in input capacitance 0 2 pf c pd power dissipation capacitance 3.3 note 4 14 pf figure 15 5.0 17 note: 4. c pd is defined as the value of the internal equivalent capacitance which is deriv ed from dynamic operating current consumption (i ccd ) at no output loading and operat ing at 50% duty cycle. (see figure 12) c pd is related to i ccd dynamic operatic current by the expression: i ccd = (c pd )(v cc )(f in ) + (i ccstatic ).
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 9 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates ac loadings and waveforms note: 5. c l includes load and stray capacitance. 6. input prr = 1.0mhz, t w = 500ns. figure 14. ac test circuit note: 7. input = ac waveforms. 8. prr = variable; duty cycle = 50%. figure 15. i ccd test circuit figure 16. ac waveforms
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 10 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates physical dimensions detail a scale: 60x b 1.90 2.00 0.20 0.50 min 1.00 0.80 1.10 0.80 0.10 c 0.25 0.10 0.46 0.26 0.20 gage plane (r0.10) 30 0 seating plane c 0.10 0.00 notes: unless otherwise specified a) this package conforms to eiaj sc-88, 1996. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. d) drawing filename: mkt-maa06arev6 2.100.30 0.10 ab 0.65 1.30 (0.25) 0.30 0.15 1 1.25 0.10 3 1.30 0.40 min see detail a land pattern recommendation 6 a 4 c 0.65 l symm pin one figure 17. 6-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf package designator tape section cavity number cavity status cover type status p6x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 11 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates physical dimensions 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 18. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 12 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 6 54 0.35 (0.08) 4x side view figure 19. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2000 fairchild semiconductor corporation www.fairchildsemi.com nc7sz57 ? nc7sz58 ? rev. 1.0.4 13 nc7sz57 / nc7sz58 ? tinylogic ? uhs universal configurat ion two-input logic gates

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